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linux-headers-5.4.0-198 /
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unaligned
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8250_pci.h
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a.out.h
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acct.h
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acpi.h
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acpi_dma.h
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acpi_iort.h
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acpi_pmtmr.h
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adb.h
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adfs_fs.h
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adxl.h
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aer.h
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agp_backend.h
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agpgart.h
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ahci-remap.h
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ahci_platform.h
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aio.h
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alarmtimer.h
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alcor_pci.h
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altera_jtaguart.h
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altera_uart.h
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amd-iommu.h
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anon_inodes.h
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apm-emulation.h
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apm_bios.h
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apple-gmux.h
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apple_bl.h
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arch_topology.h
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arm-cci.h
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arm-smccc.h
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arm_sdei.h
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armada-37xx-rwtm-mailbox.h
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ascii85.h
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asn1.h
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asn1_ber_bytecode.h
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asn1_decoder.h
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assoc_array.h
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assoc_array_priv.h
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async.h
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async_tx.h
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ata.h
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ata_platform.h
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atalk.h
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ath9k_platform.h
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atm.h
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atm_suni.h
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atm_tcp.h
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atmdev.h
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atmel-mci.h
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atmel-ssc.h
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atmel_pdc.h
1.26
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atomic-fallback.h
52.3
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atomic.h
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attribute_container.h
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audit.h
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auto_dev-ioctl.h
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auto_fs.h
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auxvec.h
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average.h
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b1pcmcia.h
666
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backing-dev-defs.h
9.33
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backing-dev.h
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backlight.h
6.37
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badblocks.h
2.14
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balloon_compaction.h
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bcd.h
559
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bch.h
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bcm47xx_nvram.h
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bcm47xx_sprom.h
386
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bcm47xx_wdt.h
555
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bcm963xx_nvram.h
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bcm963xx_tag.h
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binfmts.h
5.15
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bio.h
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bit_spinlock.h
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bitfield.h
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bitmap.h
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bitops.h
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bitrev.h
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bits.h
883
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blk-cgroup.h
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blk-mq-pci.h
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blk-mq-rdma.h
273
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blk-mq-virtio.h
293
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blk-mq.h
11.4
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blk-pm.h
717
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blk_types.h
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blkdev.h
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blkpg.h
436
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blktrace_api.h
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blockgroup_lock.h
810
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bma150.h
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bottom_half.h
803
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bpf-cgroup.h
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bpf.h
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bpf_lirc.h
698
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bpf_trace.h
166
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bpf_types.h
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bpf_verifier.h
15.18
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bpfilter.h
728
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brcmphy.h
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bsearch.h
275
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bsg-lib.h
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bsg.h
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btf.h
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btree-128.h
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btree-type.h
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btree.h
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btrfs.h
145
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buffer_head.h
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bug.h
1.92
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build-salt.h
375
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build_bug.h
2.86
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bvec.h
4.72
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c2port.h
1.35
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cache.h
2.13
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cacheinfo.h
3.32
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capability.h
7.79
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cb710.h
5.36
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cciss_ioctl.h
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ccp.h
18.12
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cdev.h
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cdrom.h
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cfag12864b.h
1.46
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cgroup-defs.h
26.87
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cgroup.h
28.89
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cgroup_rdma.h
1.18
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cgroup_subsys.h
1.17
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circ_buf.h
1.09
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cleancache.h
3.89
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clk-provider.h
40.26
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clk.h
31.76
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clkdev.h
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clock_cooling.h
1.65
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clockchips.h
7.27
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clocksource.h
8.56
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cm4000_cs.h
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cma.h
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cmdline-parser.h
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cn_proc.h
1.85
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cnt32_to_63.h
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coda.h
2.16
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compaction.h
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compat.h
31.51
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compiler-clang.h
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compiler-gcc.h
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compiler-intel.h
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compiler.h
13.4
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compiler_attributes.h
11.49
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compiler_types.h
7.44
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completion.h
4.05
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component.h
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configfs.h
8.56
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connector.h
3.8
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console.h
7.45
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console_struct.h
6.79
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consolemap.h
1.04
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const.h
157
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container.h
610
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context_tracking.h
4.43
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context_tracking_state.h
1.39
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cordic.h
2.08
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coredump.h
797
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coresight-pmu.h
989
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coresight-stm.h
152
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coresight.h
10.2
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count_zeros.h
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counter.h
16.86
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counter_enum.h
1.43
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cper.h
15.64
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cpu.h
7.63
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cpu_cooling.h
1.72
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cpu_pm.h
2.38
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cpu_rmap.h
1.68
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cpufeature.h
1.71
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cpufreq.h
30.02
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cpuhotplug.h
12.32
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cpuidle.h
9.81
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cpuidle_haltpoll.h
312
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cpumask.h
26.36
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cpuset.h
7.29
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crash_core.h
3.06
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crash_dump.h
4.02
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crc-ccitt.h
609
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crc-itu-t.h
531
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crc-t10dif.h
453
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crc16.h
540
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crc32.h
2.83
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crc32c.h
331
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crc32poly.h
610
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crc4.h
192
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crc64.h
280
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crc7.h
316
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crc8.h
3.65
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cred.h
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crypto.h
63.01
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cryptohash.h
319
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cs5535.h
6.13
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ctype.h
1.75
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cuda.h
613
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cyclades.h
10.36
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davinci_emac.h
1.05
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dax.h
7.21
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dca.h
1.88
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dcache.h
18.32
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dccp.h
10.73
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dcookies.h
1.3
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debug_locks.h
1.54
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debugfs.h
11.28
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debugobjects.h
3.89
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delay.h
1.88
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delayacct.h
5.26
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delayed_call.h
709
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devcoredump.h
2.21
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devfreq-event.h
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devfreq.h
13.06
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devfreq_cooling.h
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device-mapper.h
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device.h
67.82
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device_cgroup.h
1.86
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devpts_fs.h
1.13
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digsig.h
1.19
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dim.h
8.81
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dio.h
10.97
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dirent.h
216
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dlm.h
5.86
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dlm_plock.h
532
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dm-bufio.h
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dm-dirty-log.h
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dm-io.h
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dm-kcopyd.h
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dm-region-hash.h
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dm9000.h
987
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dma-buf.h
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dma-contiguous.h
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dma-debug.h
4.18
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dma-direct.h
2.69
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dma-direction.h
220
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dma-fence-array.h
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dma-fence-chain.h
2.04
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dma-fence.h
19.71
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dma-iommu.h
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dma-mapping.h
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dma-noncoherent.h
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dma-resv.h
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dmaengine.h
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dmapool.h
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dmar.h
7.5
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dmi.h
4.07
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dnotify.h
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dns_resolver.h
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dqblk_qtree.h
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dqblk_v1.h
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dqblk_v2.h
406
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drbd.h
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drbd_genl.h
21.49
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drbd_genl_api.h
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drbd_limits.h
7.82
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ds2782_battery.h
158
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dtlk.h
3.5
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dw_apb_timer.h
1.56
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dynamic_debug.h
6.06
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dynamic_queue_limits.h
3.7
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earlycpio.h
359
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ecryptfs.h
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edac.h
20.33
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edd.h
1.05
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eeprom_93cx6.h
2.31
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eeprom_93xx46.h
879
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efi-bgrt.h
644
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efi.h
53.96
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efs_vh.h
1.55
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eisa.h
2.96
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elevator.h
5.37
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elf-fdpic.h
1.98
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elf-randomize.h
583
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elf.h
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elfcore-compat.h
1.23
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elfcore.h
2.52
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elfnote.h
3.54
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enclosure.h
4.02
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energy_model.h
6.47
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err.h
1.55
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errno.h
1.39
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export.h
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ext2_fs.h
967
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extable.h
1.06
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27.82
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firewire.h
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firmware.h
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flat.h
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freezer.h
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fs.h
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7.8
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3.38
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4.6
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3.87
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4.16
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2.76
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fsnotify_backend.h
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fsverity.h
5.97
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30.13
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ftrace_irq.h
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gameport.h
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genetlink.h
1.35
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genhd.h
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genl_magic_func.h
11.59
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getcpu.h
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goldfish.h
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gpio-pxa.h
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gpio.h
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gpio_keys.h
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greybus.h
4.14
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hardirq.h
1.95
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hash.h
3
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hashtable.h
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3.19
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6.32
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hdmi.h
12.26
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highuid.h
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5.13
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hmm.h
14.21
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host1x.h
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hp_sdc.h
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hrtimer_defs.h
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htcpld.h
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2.93
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hw_random.h
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hwmon-sysfs.h
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hwmon-vid.h
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hwmon.h
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hwspinlock.h
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hyperv.h
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hypervisor.h
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1.4
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2.89
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438
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ieee80211.h
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ieee802154.h
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in6.h
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inet.h
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inet_diag.h
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inetdevice.h
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init.h
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init_ohci1394_dma.h
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init_task.h
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initrd.h
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inotify.h
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input-polldev.h
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input.h
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integrity.h
1.13
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intel-iommu.h
22.91
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intel-ish-client-if.h
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intel-pti.h
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intel-svm.h
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intel_rapl.h
4.12
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interconnect-provider.h
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interconnect.h
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interrupt.h
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interval_tree.h
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interval_tree_generic.h
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io-64-nonatomic-lo-hi.h
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io-mapping.h
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ioc3.h
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iocontext.h
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iomap.h
7.18
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iommu-helper.h
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iommu.h
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iopoll.h
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ioprio.h
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ipc.h
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ipc_namespace.h
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ipmi.h
10.85
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ipmi_smi.h
7.98
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ipv6.h
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ipv6_route.h
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irq.h
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irq_cpustat.h
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irq_poll.h
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irq_sim.h
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irq_work.h
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irqbypass.h
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irqchip.h
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irqdesc.h
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irqdomain.h
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irqflags.h
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irqhandler.h
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irqnr.h
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irqreturn.h
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jiffies.h
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journal-head.h
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joystick.h
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kernel-page-flags.h
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kernel.h
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kernel_stat.h
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kernelcapi.h
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kernfs.h
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kexec.h
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key-type.h
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key.h
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keyboard.h
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keyctl.h
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kfifo.h
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kgdb.h
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khugepaged.h
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klist.h
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kmemleak.h
3.27
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kobject_ns.h
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ktime.h
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kvm_host.h
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kvm_irqfd.h
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kvm_para.h
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lapb.h
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latencytop.h
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lcd.h
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lcm.h
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led-class-flash.h
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3.7
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493
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950
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2.35
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866
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leds-regulator.h
1.14
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433
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leds-ti-lmu-common.h
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leds.h
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leds_pwm.h
407
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libata.h
65.1
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libps2.h
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license.h
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lightnvm.h
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limits.h
1.05
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linkage.h
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linkmode.h
1.95
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linux_logo.h
1.91
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lis3lv02d.h
5
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list.h
26.9
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list_bl.h
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list_lru.h
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list_nulls.h
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list_sort.h
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livepatch.h
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llc.h
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llist.h
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lockdep.h
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lockref.h
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log2.h
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logic_pio.h
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lp.h
2.76
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lru_cache.h
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lsm_audit.h
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lsm_hooks.h
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5.39
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14.91
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mailbox_client.h
1.71
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mailbox_controller.h
5.7
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maple.h
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marvell_phy.h
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math64.h
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max17040_battery.h
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mbcache.h
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mbus.h
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mc146818rtc.h
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mc6821.h
1.18
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3.71
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5.21
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mdio-bitbang.h
1.12
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mdio-gpio.h
177
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mdio-mux.h
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mdio.h
10.86
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mei_cl_bus.h
3.43
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mem_encrypt.h
885
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memblock.h
18.46
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memcontrol.h
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memfd.h
365
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memory.h
4.74
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memory_hotplug.h
10.96
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mempolicy.h
7.44
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mempool.h
3.35
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memremap.h
5.36
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memstick.h
9.6
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mic_bus.h
2.7
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micrel_phy.h
1.28
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microchipphy.h
2.65
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migrate.h
5.96
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migrate_mode.h
758
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mii.h
14.04
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miscdevice.h
2.81
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mm-arch-hooks.h
533
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mm.h
92.34
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mm_inline.h
3.37
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mm_types.h
23.61
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mm_types_task.h
2.5
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mman.h
3.28
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mmap_lock.h
1.06
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mmdebug.h
2.32
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mmiotrace.h
3.05
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mmu_context.h
378
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mmu_notifier.h
19.84
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mmzone.h
41.85
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mnt_namespace.h
617
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mod_devicetable.h
21.91
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module.h
24.34
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module_signature.h
1.22
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moduleloader.h
2.87
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moduleparam.h
19.53
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mount.h
3.64
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moxtet.h
2.37
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mpage.h
761
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mpi.h
2.51
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mpls.h
394
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mpls_iptunnel.h
178
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mroute.h
1.95
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mroute6.h
2.39
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mroute_base.h
12.03
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msdos_fs.h
273
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msg.h
395
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msi.h
12.84
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mutex.h
6.55
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mv643xx.h
51.27
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mv643xx_eth.h
1.95
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mv643xx_i2c.h
335
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mvebu-pmsu.h
520
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mxm-wmi.h
399
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n_r3964.h
4.06
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namei.h
3.34
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nd.h
5.52
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ndctl.h
674
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net.h
11.75
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netdev_features.h
9.7
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netdevice.h
152.29
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netfilter.h
13.36
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netfilter_bridge.h
2.08
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netfilter_defs.h
242
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netfilter_ingress.h
1.44
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netfilter_ipv4.h
1.05
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netfilter_ipv6.h
5.85
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netlink.h
7.19
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netpoll.h
2.69
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nfs.h
1.31
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nfs3.h
260
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nfs4.h
17.86
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nfs_fs.h
17.2
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nfs_fs_i.h
308
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nfs_fs_sb.h
9.54
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nfs_iostat.h
4.18
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nfs_page.h
6.38
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nfs_xdr.h
40.17
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nfsacl.h
1.15
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nl802154.h
3.85
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nls.h
3.09
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nmi.h
6.86
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node.h
4.69
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nodemask.h
17.1
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nospec.h
2.21
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notifier.h
8.21
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ns_common.h
235
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nsc_gpio.h
1.42
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nsproxy.h
2.48
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ntb.h
52.43
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ntb_transport.h
3.8
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nubus.h
5.54
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numa.h
292
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nvme-fc-driver.h
37.18
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nvme-fc.h
9.69
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nvme-rdma.h
2.04
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nvme-tcp.h
4.42
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nvme.h
33.32
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nvmem-consumer.h
5.8
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nvmem-provider.h
3.88
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nvram.h
3.47
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objagg.h
1.99
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of.h
42.38
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of_address.h
4.47
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of_clk.h
795
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of_device.h
2.99
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of_dma.h
2.3
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of_fdt.h
3.69
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of_gpio.h
3.96
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of_graph.h
3.41
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of_iommu.h
821
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of_irq.h
3.62
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of_mdio.h
2.98
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of_net.h
720
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of_pci.h
935
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of_pdt.h
1.14
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of_platform.h
3.88
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of_reserved_mem.h
2.15
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oid_registry.h
4.44
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olpc-ec.h
1.95
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omap-dma.h
10.47
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omap-gpmc.h
2.73
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omap-iommu.h
880
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omap-mailbox.h
689
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omapfb.h
576
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once.h
2.79
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3.26
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openvswitch.h
403
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oprofile.h
6.1
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osq_lock.h
1.04
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overflow.h
9.58
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packing.h
1.78
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padata.h
6.35
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page-flags-layout.h
3.28
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page-flags.h
27.15
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page-isolation.h
1.65
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page_counter.h
1.94
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page_ext.h
1.68
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page_idle.h
2.62
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page_owner.h
2.29
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page_ref.h
4.99
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pageblock-flags.h
2.72
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pagemap.h
18.76
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pagevec.h
2.34
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pagewalk.h
2.39
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parman.h
2.87
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parport.h
17.84
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parport_pc.h
6.56
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parser.h
1.04
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pata_arasan_cf_data.h
1.22
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patchkey.h
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path.h
572
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pch_dma.h
408
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pci-acpi.h
3.48
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pci-ats.h
1.52
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pci-dma-compat.h
3.66
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pci-ecam.h
2.19
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pci-ep-cfs.h
951
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pci-epc.h
6.93
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pci-epf.h
4.75
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pci-p2pdma.h
3.95
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pci.h
86.3
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pci_hotplug.h
4.25
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pci_ids.h
121.42
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pda_power.h
1005
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pe.h
15.05
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percpu-defs.h
18.12
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percpu-refcount.h
10.46
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percpu-rwsem.h
3.93
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percpu.h
4.65
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percpu_counter.h
4.27
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perf_event.h
42.54
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perf_regs.h
1.13
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personality.h
393
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pfn.h
666
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pfn_t.h
3.21
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phonet.h
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phy.h
40.59
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phy_fixed.h
1.77
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phy_led_triggers.h
1.01
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phylink.h
10.47
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pid.h
5.85
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pid_namespace.h
2.33
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pim.h
2.67
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pipe_fs_i.h
6.17
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pkeys.h
1016
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pktcdvd.h
5.87
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pl320-ipc.h
209
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pl353-smc.h
739
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platform_device.h
13.05
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plist.h
8.66
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pm-trace.h
940
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pm.h
33.27
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pm2301_charger.h
1.09
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pm_clock.h
2.45
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pm_domain.h
11.74
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pm_opp.h
11.41
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pm_qos.h
9.83
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pm_runtime.h
9.56
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pm_wakeirq.h
1.48
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pm_wakeup.h
5.74
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pmbus.h
970
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pmu.h
2.44
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pnfs_osd_xdr.h
9.27
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pnp.h
14.89
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poison.h
2.56
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poll.h
4.01
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posix-clock.h
3.91
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posix-timers.h
6.31
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posix_acl.h
3.09
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posix_acl_xattr.h
1.58
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power_supply.h
16.06
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powercap.h
12.04
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ppp-comp.h
2.95
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ppp_channel.h
2.87
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ppp_defs.h
305
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pps-gpio.h
395
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pps_kernel.h
2.9
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pr.h
566
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prandom.h
3.38
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preempt.h
10
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prefetch.h
1.7
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prime_numbers.h
1.35
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printk.h
15.92
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proc_fs.h
6.58
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proc_ns.h
2.6
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processor.h
1.84
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profile.h
2.68
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projid.h
2.22
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property.h
14.29
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psci.h
1.48
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pseudo_fs.h
355
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psi.h
1.53
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psi_types.h
3.53
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psp-sev.h
17.04
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pstore.h
7.28
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pstore_ram.h
3.81
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pti.h
240
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ptp_classify.h
2.33
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ptp_clock_kernel.h
9.01
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ptr_ring.h
16.27
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ptrace.h
14.65
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purgatory.h
589
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pvclock_gtod.h
548
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pwm.h
16.08
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pwm_backlight.h
802
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pxa168_eth.h
728
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pxa2xx_ssp.h
9.85
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qcom-geni-se.h
12.21
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qcom_scm.h
4.09
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qnx6_fs.h
3.27
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quota.h
18.7
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quotaops.h
10.37
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radix-tree.h
15.61
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raid_class.h
2
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ramfs.h
659
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random.h
3.98
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range.h
651
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ras.h
1.18
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ratelimit.h
2.81
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rational.h
639
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rbtree.h
5.09
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rbtree_augmented.h
9.6
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rbtree_latch.h
6.64
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rcu_node_tree.h
3.7
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rcu_segcblist.h
2.77
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rcu_sync.h
1.46
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rculist.h
25.42
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rculist_bl.h
4.36
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rculist_nulls.h
6.17
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rcupdate.h
34.54
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rcupdate_wait.h
897
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rcutiny.h
2.58
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rcutree.h
1.93
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rcuwait.h
1.23
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reboot-mode.h
600
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reboot.h
2.11
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reciprocal_div.h
3.28
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refcount.h
10.3
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regmap.h
52.3
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regset.h
14.92
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relay.h
8.84
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remoteproc.h
22.07
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reset-controller.h
3.03
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reset.h
15.74
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resource.h
339
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resource_ext.h
1.83
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restart_block.h
1.09
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rfkill.h
9.86
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rhashtable-types.h
3.45
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rhashtable.h
37.82
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ring_buffer.h
7.27
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rio.h
19.02
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rio_drv.h
14.5
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rio_ids.h
1.08
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rio_regs.h
19.07
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rmap.h
9.08
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rmi.h
12.02
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rndis.h
16.86
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rodata_test.h
394
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root_dev.h
619
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rpmsg.h
7.3
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rslib.h
3.67
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rtc.h
9
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rtmutex.h
3.47
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rtnetlink.h
4.46
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rtsx_common.h
890
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rtsx_pci.h
39.6
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rtsx_usb.h
15.38
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rwlock.h
4.35
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rwlock_api_smp.h
7.67
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rwlock_types.h
1.12
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rwsem.h
6.4
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s3c_adc_battery.h
971
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sbitmap.h
16.52
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scatterlist.h
16.16
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scc.h
2.84
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sched.h
55.47
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sched_clock.h
520
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scif.h
58.87
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scmi_protocol.h
10.44
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scpi_protocol.h
2.04
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screen_info.h
191
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sctp.h
21.99
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scx200.h
1.82
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scx200_gpio.h
2.38
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sdb.h
4.17
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sdla.h
6.69
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seccomp.h
2.94
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securebits.h
239
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security.h
51.54
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sed-opal.h
1.62
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seg6.h
121
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seg6_genl.h
136
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seg6_hmac.h
136
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seg6_iptunnel.h
148
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seg6_local.h
100
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selection.h
1.74
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Code Editor : clk-provider.h
/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> */ #ifndef __LINUX_CLK_PROVIDER_H #define __LINUX_CLK_PROVIDER_H #include <linux/of.h> #include <linux/of_clk.h> /* * flags used across common struct clk. these flags should only affect the * top-level framework. custom flags for dealing with hardware specifics * belong in struct clk_foo * * Please update clk_flags[] in drivers/clk/clk.c when making changes here! */ #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ /* unused */ /* unused */ #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ /* parents need enable during gate/ungate, set rate and re-parent */ #define CLK_OPS_PARENT_ENABLE BIT(12) /* duty cycle call may be forwarded to the parent clock */ #define CLK_DUTY_CYCLE_PARENT BIT(13) struct clk; struct clk_hw; struct clk_core; struct dentry; /** * struct clk_rate_request - Structure encoding the clk constraints that * a clock user might require. * * @rate: Requested clock rate. This field will be adjusted by * clock drivers according to hardware capabilities. * @min_rate: Minimum rate imposed by clk users. * @max_rate: Maximum rate imposed by clk users. * @best_parent_rate: The best parent rate a parent can provide to fulfill the * requested constraints. * @best_parent_hw: The most appropriate parent clock that fulfills the * requested constraints. * */ struct clk_rate_request { unsigned long rate; unsigned long min_rate; unsigned long max_rate; unsigned long best_parent_rate; struct clk_hw *best_parent_hw; }; /** * struct clk_duty - Struture encoding the duty cycle ratio of a clock * * @num: Numerator of the duty cycle ratio * @den: Denominator of the duty cycle ratio */ struct clk_duty { unsigned int num; unsigned int den; }; /** * struct clk_ops - Callback operations for hardware clocks; these are to * be provided by the clock implementation, and will be called by drivers * through the clk_* api. * * @prepare: Prepare the clock for enabling. This must not return until * the clock is fully prepared, and it's safe to call clk_enable. * This callback is intended to allow clock implementations to * do any initialisation that may sleep. Called with * prepare_lock held. * * @unprepare: Release the clock from its prepared state. This will typically * undo any work done in the @prepare callback. Called with * prepare_lock held. * * @is_prepared: Queries the hardware to determine if the clock is prepared. * This function is allowed to sleep. Optional, if this op is not * set then the prepare count will be used. * * @unprepare_unused: Unprepare the clock atomically. Only called from * clk_disable_unused for prepare clocks with special needs. * Called with prepare mutex held. This function may sleep. * * @enable: Enable the clock atomically. This must not return until the * clock is generating a valid clock signal, usable by consumer * devices. Called with enable_lock held. This function must not * sleep. * * @disable: Disable the clock atomically. Called with enable_lock held. * This function must not sleep. * * @is_enabled: Queries the hardware to determine if the clock is enabled. * This function must not sleep. Optional, if this op is not * set then the enable count will be used. * * @disable_unused: Disable the clock atomically. Only called from * clk_disable_unused for gate clocks with special needs. * Called with enable_lock held. This function must not * sleep. * * @save_context: Save the context of the clock in prepration for poweroff. * * @restore_context: Restore the context of the clock after a restoration * of power. * * @recalc_rate Recalculate the rate of this clock, by querying hardware. The * parent rate is an input parameter. It is up to the caller to * ensure that the prepare_mutex is held across this call. * Returns the calculated rate. Optional, but recommended - if * this op is not set then clock rate will be initialized to 0. * * @round_rate: Given a target rate as input, returns the closest rate actually * supported by the clock. The parent rate is an input/output * parameter. * * @determine_rate: Given a target rate as input, returns the closest rate * actually supported by the clock, and optionally the parent clock * that should be used to provide the clock rate. * * @set_parent: Change the input source of this clock; for clocks with multiple * possible parents specify a new parent by passing in the index * as a u8 corresponding to the parent in either the .parent_names * or .parents arrays. This function in affect translates an * array index into the value programmed into the hardware. * Returns 0 on success, -EERROR otherwise. * * @get_parent: Queries the hardware to determine the parent of a clock. The * return value is a u8 which specifies the index corresponding to * the parent clock. This index can be applied to either the * .parent_names or .parents arrays. In short, this function * translates the parent value read from hardware into an array * index. Currently only called when the clock is initialized by * __clk_init. This callback is mandatory for clocks with * multiple parents. It is optional (and unnecessary) for clocks * with 0 or 1 parents. * * @set_rate: Change the rate of this clock. The requested rate is specified * by the second argument, which should typically be the return * of .round_rate call. The third argument gives the parent rate * which is likely helpful for most .set_rate implementation. * Returns 0 on success, -EERROR otherwise. * * @set_rate_and_parent: Change the rate and the parent of this clock. The * requested rate is specified by the second argument, which * should typically be the return of .round_rate call. The * third argument gives the parent rate which is likely helpful * for most .set_rate_and_parent implementation. The fourth * argument gives the parent index. This callback is optional (and * unnecessary) for clocks with 0 or 1 parents as well as * for clocks that can tolerate switching the rate and the parent * separately via calls to .set_parent and .set_rate. * Returns 0 on success, -EERROR otherwise. * * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy * is expressed in ppb (parts per billion). The parent accuracy is * an input parameter. * Returns the calculated accuracy. Optional - if this op is not * set then clock accuracy will be initialized to parent accuracy * or 0 (perfect clock) if clock has no parent. * * @get_phase: Queries the hardware to get the current phase of a clock. * Returned values are 0-359 degrees on success, negative * error codes on failure. * * @set_phase: Shift the phase this clock signal in degrees specified * by the second argument. Valid values for degrees are * 0-359. Return 0 on success, otherwise -EERROR. * * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio * of a clock. Returned values denominator cannot be 0 and must be * superior or equal to the numerator. * * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by * the numerator (2nd argurment) and denominator (3rd argument). * Argument must be a valid ratio (denominator > 0 * and >= numerator) Return 0 on success, otherwise -EERROR. * * @init: Perform platform-specific initialization magic. * This is not not used by any of the basic clock types. * Please consider other ways of solving initialization problems * before using this callback, as its use is discouraged. * * @debug_init: Set up type-specific debugfs entries for this clock. This * is called once, after the debugfs directory entry for this * clock has been created. The dentry pointer representing that * directory is provided as an argument. Called with * prepare_lock held. Returns 0 on success, -EERROR otherwise. * * * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow * implementations to split any work between atomic (enable) and sleepable * (prepare) contexts. If enabling a clock requires code that might sleep, * this must be done in clk_prepare. Clock enable code that will never be * called in a sleepable context may be implemented in clk_enable. * * Typically, drivers will call clk_prepare when a clock may be needed later * (eg. when a device is opened), and clk_enable when the clock is actually * required (eg. from an interrupt). Note that clk_prepare MUST have been * called before clk_enable. */ struct clk_ops { int (*prepare)(struct clk_hw *hw); void (*unprepare)(struct clk_hw *hw); int (*is_prepared)(struct clk_hw *hw); void (*unprepare_unused)(struct clk_hw *hw); int (*enable)(struct clk_hw *hw); void (*disable)(struct clk_hw *hw); int (*is_enabled)(struct clk_hw *hw); void (*disable_unused)(struct clk_hw *hw); int (*save_context)(struct clk_hw *hw); void (*restore_context)(struct clk_hw *hw); unsigned long (*recalc_rate)(struct clk_hw *hw, unsigned long parent_rate); long (*round_rate)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate); int (*determine_rate)(struct clk_hw *hw, struct clk_rate_request *req); int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); int (*set_rate_and_parent)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index); unsigned long (*recalc_accuracy)(struct clk_hw *hw, unsigned long parent_accuracy); int (*get_phase)(struct clk_hw *hw); int (*set_phase)(struct clk_hw *hw, int degrees); int (*get_duty_cycle)(struct clk_hw *hw, struct clk_duty *duty); int (*set_duty_cycle)(struct clk_hw *hw, struct clk_duty *duty); void (*init)(struct clk_hw *hw); void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); }; /** * struct clk_parent_data - clk parent information * @hw: parent clk_hw pointer (used for clk providers with internal clks) * @fw_name: parent name local to provider registering clk * @name: globally unique parent name (used as a fallback) * @index: parent index local to provider registering clk (if @fw_name absent) */ struct clk_parent_data { const struct clk_hw *hw; const char *fw_name; const char *name; int index; }; /** * struct clk_init_data - holds init data that's common to all clocks and is * shared between the clock provider and the common clock framework. * * @name: clock name * @ops: operations this clock supports * @parent_names: array of string names for all possible parents * @parent_data: array of parent data for all possible parents (when some * parents are external to the clk controller) * @parent_hws: array of pointers to all possible parents (when all parents * are internal to the clk controller) * @num_parents: number of possible parents * @flags: framework-level hints and quirks */ struct clk_init_data { const char *name; const struct clk_ops *ops; /* Only one of the following three should be assigned */ const char * const *parent_names; const struct clk_parent_data *parent_data; const struct clk_hw **parent_hws; u8 num_parents; unsigned long flags; }; /** * struct clk_hw - handle for traversing from a struct clk to its corresponding * hardware-specific structure. struct clk_hw should be declared within struct * clk_foo and then referenced by the struct clk instance that uses struct * clk_foo's clk_ops * * @core: pointer to the struct clk_core instance that points back to this * struct clk_hw instance * * @clk: pointer to the per-user struct clk instance that can be used to call * into the clk API * * @init: pointer to struct clk_init_data that contains the init data shared * with the common clock framework. This pointer will be set to NULL once * a clk_register() variant is called on this clk_hw pointer. */ struct clk_hw { struct clk_core *core; struct clk *clk; const struct clk_init_data *init; }; /* * DOC: Basic clock implementations common to many platforms * * Each basic clock hardware type is comprised of a structure describing the * clock hardware, implementations of the relevant callbacks in struct clk_ops, * unique flags for that hardware type, a registration function and an * alternative macro for static initialization */ /** * struct clk_fixed_rate - fixed-rate clock * @hw: handle between common and hardware-specific interfaces * @fixed_rate: constant frequency of clock */ struct clk_fixed_rate { struct clk_hw hw; unsigned long fixed_rate; unsigned long fixed_accuracy; }; #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) extern const struct clk_ops clk_fixed_rate_ops; struct clk *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate); struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate); struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy); void clk_unregister_fixed_rate(struct clk *clk); struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy); void clk_hw_unregister_fixed_rate(struct clk_hw *hw); void of_fixed_clk_setup(struct device_node *np); /** * struct clk_gate - gating clock * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling gate * @bit_idx: single bit controlling gate * @flags: hardware-specific flags * @lock: register lock * * Clock which can gate its output. Implements .enable & .disable * * Flags: * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to * enable the clock. Setting this flag does the opposite: setting the bit * disable the clock and clearing it enables the clock * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit * of this register, and mask of gate bits are in higher 16-bit of this * register. While setting the gate bits, higher 16-bit should also be * updated to indicate changing gate bits. * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for * the gate register. Setting this flag makes the register accesses big * endian. */ struct clk_gate { struct clk_hw hw; void __iomem *reg; u8 bit_idx; u8 flags; spinlock_t *lock; }; #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) #define CLK_GATE_BIG_ENDIAN BIT(2) extern const struct clk_ops clk_gate_ops; struct clk *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); struct clk_div_table { unsigned int val; unsigned int div; }; /** * struct clk_divider - adjustable divider clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the divider * @shift: shift to the divider bit field * @width: width of the divider bit field * @table: array of value/divider pairs, last entry should have div = 0 * @lock: register lock * * Clock with an adjustable divider affecting its output frequency. Implements * .recalc_rate, .set_rate and .round_rate * * Flags: * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is * the raw value read from the register, with the value of zero considered * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from * the hardware register * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. * Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit * of this register, and mask of divider bits are in higher 16-bit of this * register. While setting the divider bits, higher 16-bit should also be * updated to indicate changing divider bits. * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded * to the closest integer instead of the up one. * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should * not be changed by the clock framework. * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED * except when the value read from the register is zero, the divisor is * 2^width of the field. * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used * for the divider register. Setting this flag makes the register accesses * big endian. */ struct clk_divider { struct clk_hw hw; void __iomem *reg; u8 shift; u8 width; u8 flags; const struct clk_div_table *table; spinlock_t *lock; }; #define clk_div_mask(width) ((1 << (width)) - 1) #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) #define CLK_DIVIDER_ALLOW_ZERO BIT(2) #define CLK_DIVIDER_HIWORD_MASK BIT(3) #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) #define CLK_DIVIDER_BIG_ENDIAN BIT(7) extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, unsigned int val, const struct clk_div_table *table, unsigned long flags, unsigned long width); long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags); long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags, unsigned int val); int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width, unsigned long flags); struct clk *clk_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, spinlock_t *lock); struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, spinlock_t *lock); struct clk *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); struct clk_hw *clk_hw_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); void clk_unregister_divider(struct clk *clk); void clk_hw_unregister_divider(struct clk_hw *hw); /** * struct clk_mux - multiplexer clock * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling multiplexer * @table: array of register values corresponding to the parent index * @shift: shift to multiplexer bit field * @mask: mask of mutliplexer bit field * @flags: hardware-specific flags * @lock: register lock * * Clock with multiple selectable parents. Implements .get_parent, .set_parent * and .recalc_rate * * Flags: * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this * register, and mask of mux bits are in higher 16-bit of this register. * While setting the mux bits, higher 16-bit should also be updated to * indicate changing mux bits. * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the * .get_parent clk_op. * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired * frequency. * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for * the mux register. Setting this flag makes the register accesses big * endian. */ struct clk_mux { struct clk_hw hw; void __iomem *reg; u32 *table; u32 mask; u8 shift; u8 flags; spinlock_t *lock; }; #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) #define CLK_MUX_INDEX_ONE BIT(0) #define CLK_MUX_INDEX_BIT BIT(1) #define CLK_MUX_HIWORD_MASK BIT(2) #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ #define CLK_MUX_ROUND_CLOSEST BIT(4) #define CLK_MUX_BIG_ENDIAN BIT(5) extern const struct clk_ops clk_mux_ops; extern const struct clk_ops clk_mux_ro_ops; struct clk *clk_register_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock); struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock); struct clk *clk_register_mux_table(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, unsigned int val); unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index); void clk_unregister_mux(struct clk *clk); void clk_hw_unregister_mux(struct clk_hw *hw); void of_fixed_factor_clk_setup(struct device_node *node); /** * struct clk_fixed_factor - fixed multiplier and divider clock * * @hw: handle between common and hardware-specific interfaces * @mult: multiplier * @div: divider * * Clock with a fixed multiplier and divider. The output frequency is the * parent clock rate divided by div and multiplied by mult. * Implements .recalc_rate, .set_rate and .round_rate */ struct clk_fixed_factor { struct clk_hw hw; unsigned int mult; unsigned int div; }; #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) extern const struct clk_ops clk_fixed_factor_ops; struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); void clk_unregister_fixed_factor(struct clk *clk); struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); /** * struct clk_fractional_divider - adjustable fractional divider clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the divider * @mshift: shift to the numerator bit field * @mwidth: width of the numerator bit field * @nshift: shift to the denominator bit field * @nwidth: width of the denominator bit field * @lock: register lock * * Clock with adjustable fractional divider affecting its output frequency. * * Flags: * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED * is set then the numerator and denominator are both the value read * plus one. * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are * used for the divider register. Setting this flag makes the register * accesses big endian. */ struct clk_fractional_divider { struct clk_hw hw; void __iomem *reg; u8 mshift; u8 mwidth; u32 mmask; u8 nshift; u8 nwidth; u32 nmask; u8 flags; void (*approximation)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate, unsigned long *m, unsigned long *n); spinlock_t *lock; }; #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock); struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock); void clk_hw_unregister_fractional_divider(struct clk_hw *hw); /** * struct clk_multiplier - adjustable multiplier clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the multiplier * @shift: shift to the multiplier bit field * @width: width of the multiplier bit field * @lock: register lock * * Clock with an adjustable multiplier affecting its output frequency. * Implements .recalc_rate, .set_rate and .round_rate * * Flags: * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read * from the register, with 0 being a valid value effectively * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is * set, then a null multiplier will be considered as a bypass, * leaving the parent rate unmodified. * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be * rounded to the closest integer instead of the down one. * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are * used for the multiplier register. Setting this flag makes the register * accesses big endian. */ struct clk_multiplier { struct clk_hw hw; void __iomem *reg; u8 shift; u8 width; u8 flags; spinlock_t *lock; }; #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) extern const struct clk_ops clk_multiplier_ops; /*** * struct clk_composite - aggregate clock of mux, divider and gate clocks * * @hw: handle between common and hardware-specific interfaces * @mux_hw: handle between composite and hardware-specific mux clock * @rate_hw: handle between composite and hardware-specific rate clock * @gate_hw: handle between composite and hardware-specific gate clock * @mux_ops: clock ops for mux * @rate_ops: clock ops for rate * @gate_ops: clock ops for gate */ struct clk_composite { struct clk_hw hw; struct clk_ops ops; struct clk_hw *mux_hw; struct clk_hw *rate_hw; struct clk_hw *gate_hw; const struct clk_ops *mux_ops; const struct clk_ops *rate_ops; const struct clk_ops *gate_ops; }; #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) struct clk *clk_register_composite(struct device *dev, const char *name, const char * const *parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); void clk_unregister_composite(struct clk *clk); struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, const char * const *parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); void clk_hw_unregister_composite(struct clk_hw *hw); /** * struct clk_gpio - gpio gated clock * * @hw: handle between common and hardware-specific interfaces * @gpiod: gpio descriptor * * Clock with a gpio control for enabling and disabling the parent clock * or switching between two parents by asserting or deasserting the gpio. * * Implements .enable, .disable and .is_enabled or * .get_parent, .set_parent and .determine_rate depending on which clk_ops * is used. */ struct clk_gpio { struct clk_hw hw; struct gpio_desc *gpiod; }; #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) extern const struct clk_ops clk_gpio_gate_ops; struct clk *clk_register_gpio_gate(struct device *dev, const char *name, const char *parent_name, struct gpio_desc *gpiod, unsigned long flags); struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, const char *parent_name, struct gpio_desc *gpiod, unsigned long flags); void clk_hw_unregister_gpio_gate(struct clk_hw *hw); extern const struct clk_ops clk_gpio_mux_ops; struct clk *clk_register_gpio_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, unsigned long flags); struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, unsigned long flags); void clk_hw_unregister_gpio_mux(struct clk_hw *hw); struct clk *clk_register(struct device *dev, struct clk_hw *hw); struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw); void clk_unregister(struct clk *clk); void devm_clk_unregister(struct device *dev, struct clk *clk); void clk_hw_unregister(struct clk_hw *hw); void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); /* helper functions */ const char *__clk_get_name(const struct clk *clk); const char *clk_hw_get_name(const struct clk_hw *hw); #ifdef CONFIG_COMMON_CLK struct clk_hw *__clk_get_hw(struct clk *clk); #else static inline struct clk_hw *__clk_get_hw(struct clk *clk) { return (struct clk_hw *)clk; } #endif unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index); int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); unsigned int __clk_get_enable_count(struct clk *clk); unsigned long clk_hw_get_rate(const struct clk_hw *hw); unsigned long __clk_get_flags(struct clk *clk); unsigned long clk_hw_get_flags(const struct clk_hw *hw); #define clk_hw_can_set_rate_parent(hw) \ (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) bool clk_hw_is_prepared(const struct clk_hw *hw); bool clk_hw_rate_is_protected(const struct clk_hw *hw); bool clk_hw_is_enabled(const struct clk_hw *hw); bool __clk_is_enabled(struct clk *clk); struct clk *__clk_lookup(const char *name); int __clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req); int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); int __clk_mux_determine_rate_closest(struct clk_hw *hw, struct clk_rate_request *req); int clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req, unsigned long flags); void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, unsigned long max_rate); static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) { dst->clk = src->clk; dst->core = src->core; } static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags) { return divider_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags); } static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags, unsigned int val) { return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags, val); } /* * FIXME clock api without lock protection */ unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); struct clk_onecell_data { struct clk **clks; unsigned int clk_num; }; struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) /* * Use this macro when you have a driver that requires two initialization * routines, one at of_clk_init(), and one at platform device probe */ #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ static void __init name##_of_clk_init_driver(struct device_node *np) \ { \ of_node_clear_flag(np, OF_POPULATED); \ fn(np); \ } \ OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_names = (const char *[]) { _parent }, \ .num_parents = 1, \ .ops = _ops, \ }) #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_hws = (const struct clk_hw*[]) { _parent }, \ .num_parents = 1, \ .ops = _ops, \ }) /* * This macro is intended for drivers to be able to share the otherwise * individual struct clk_hw[] compound literals created by the compiler * when using CLK_HW_INIT_HW. It does NOT support multiple parents. */ #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_hws = _parent, \ .num_parents = 1, \ .ops = _ops, \ }) #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_data = (const struct clk_parent_data[]) { \ { .fw_name = _parent }, \ }, \ .num_parents = 1, \ .ops = _ops, \ }) #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_names = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ .ops = _ops, \ }) #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_hws = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ .ops = _ops, \ }) #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_data = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ .ops = _ops, \ }) #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ (&(struct clk_init_data) { \ .flags = _flags, \ .name = _name, \ .parent_names = NULL, \ .num_parents = 0, \ .ops = _ops, \ }) #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ _div, _mult, _flags) \ struct clk_fixed_factor _struct = { \ .div = _div, \ .mult = _mult, \ .hw.init = CLK_HW_INIT(_name, \ _parent, \ &clk_fixed_factor_ops, \ _flags), \ } #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \ _div, _mult, _flags) \ struct clk_fixed_factor _struct = { \ .div = _div, \ .mult = _mult, \ .hw.init = CLK_HW_INIT_HW(_name, \ _parent, \ &clk_fixed_factor_ops, \ _flags), \ } /* * This macro allows the driver to reuse the _parent array for multiple * fixed factor clk declarations. */ #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \ _div, _mult, _flags) \ struct clk_fixed_factor _struct = { \ .div = _div, \ .mult = _mult, \ .hw.init = CLK_HW_INIT_HWS(_name, \ _parent, \ &clk_fixed_factor_ops, \ _flags), \ } #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \ _div, _mult, _flags) \ struct clk_fixed_factor _struct = { \ .div = _div, \ .mult = _mult, \ .hw.init = CLK_HW_INIT_FW_NAME(_name, \ _parent, \ &clk_fixed_factor_ops, \ _flags), \ } #ifdef CONFIG_OF int of_clk_add_provider(struct device_node *np, struct clk *(*clk_src_get)(struct of_phandle_args *args, void *data), void *data); int of_clk_add_hw_provider(struct device_node *np, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data); int devm_of_clk_add_hw_provider(struct device *dev, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data); void of_clk_del_provider(struct device_node *np); void devm_of_clk_del_provider(struct device *dev); struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, void *data); struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data); struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data); int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned int size); int of_clk_detect_critical(struct device_node *np, int index, unsigned long *flags); #else /* !CONFIG_OF */ static inline int of_clk_add_provider(struct device_node *np, struct clk *(*clk_src_get)(struct of_phandle_args *args, void *data), void *data) { return 0; } static inline int of_clk_add_hw_provider(struct device_node *np, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data) { return 0; } static inline int devm_of_clk_add_hw_provider(struct device *dev, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data) { return 0; } static inline void of_clk_del_provider(struct device_node *np) {} static inline void devm_of_clk_del_provider(struct device *dev) {} static inline struct clk *of_clk_src_simple_get( struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline struct clk_hw * of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline struct clk *of_clk_src_onecell_get( struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline struct clk_hw * of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned int size) { return 0; } static inline int of_clk_detect_critical(struct device_node *np, int index, unsigned long *flags) { return 0; } #endif /* CONFIG_OF */ void clk_gate_restore_context(struct clk_hw *hw); #endif /* CLK_PROVIDER_H */
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